Title
A New Esd Design Methodology For High Voltage Dmos Applications
Abstract
A comprehensive methodology for synthesizing robust ESD performance in highly sensitive high voltage NLDMOS functional blocks is introduced. Optimizing high voltage output stage design for robust device- and system-level (IEC 61000-4-2)/HMM is assessed under 1-, 2-, 5-, 10- ,100-ns wide time frames of typical electrostatic discharge (ESD) stress models.
Publication Date
12-24-2010
Publication Title
Electrical Overstress/Electrostatic Discharge Symposium Proceedings
Document Type
Article; Proceedings Paper
Personal Identifier
scopus
Copyright Status
Unknown
Socpus ID
78650378269 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/78650378269
STARS Citation
Malobabic, Slavica; Salcedo, Javier A.; Righter, Alan W.; Hajjar, Jean Jacques; and Liou, Juin J., "A New Esd Design Methodology For High Voltage Dmos Applications" (2010). Scopus Export 2010-2014. 207.
https://stars.library.ucf.edu/scopus2010/207