Title

Design Considerations On Low Voltage Synchronous Power Mosfets With Monolithically Integrated Gate Voltage Pull-Down Circuitry

Keywords

C·dV/dt induced turn-on; integrated gate voltage pull-down circuitry; NexFET; Synchronous buck Converter

Abstract

In this paper, a monolithically integrated gate voltage pull-down circuitry is presented to avoid the unintentional C·dV/dt induced turn-on. The concept of a low threshold voltage MOSFET with this integrated gate voltage pull-down circuitry is introduced as a contributing factor to the next generation high frequency DC-DC converter efficiency improvement. Design considerations on this new device and influences of critical design parameters on device/circuit performance will be fully discussed. In synchronous buck application, this integrated power module achieves more than 2% efficiency improvement over reference solution at high operation frequency (1MHz) under 19V input and 1.3V output condition. © 2012 IEEE.

Publication Date

8-8-2012

Publication Title

Proceedings of the International Symposium on Power Semiconductor Devices and ICs

Number of Pages

121-124

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISPSD.2012.6229038

Socpus ID

84864762403 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84864762403

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