Title

Exploiting Memory-Level Parallelism In Reconfigurable Accelerators

Keywords

Application-Specific; FPGA; High-level synthesis; Memory Structure; Memory-Level Parallelism; Reconfigurable

Abstract

As memory accesses increasingly limit the overall performance of reconfigurable accelerators, it is important for high level synthesis (HLS) flows to discover and exploit memory-level parallelism. This paper develops 1) a framework where parallelism between memory accesses can be revealed from runtime profile of applications and provided to a high level synthesis flow, and 2) a novel multi-accelerator/multi-cache architecture to support parallel memory accesses, taking advantage of the high aggregated memory bandwidth found in modern FPGA devices. Our experimental results have shown that for 10 accelerators generated from 9 benchmark applications, circuits using our proposed memory structure achieve on average 52% improved performance over accelerators using a traditional memory interface. We believe that our study represents a solid advance towards achieving memory-parallel embedded computing on hybrid CPU+FPGA platforms. © 2012 IEEE.

Publication Date

8-17-2012

Publication Title

Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012

Number of Pages

157-160

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/FCCM.2012.35

Socpus ID

84864915881 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84864915881

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