Title

Characterization Of Silicon Nanowires Grown By Electroless Etching

Keywords

Collector-Emitter Saturation Voltage; Conduction Losses; Hole Barrier; Insulated Gate Bipolar Transistor (IGBT); P+ Plug; Short Circuit Ruggedness

Abstract

A new device structure for enhancing conductivity modulation in the Insulated Gate Bipolar Transistor (IGBT) is numerically studied. An N-type hole barrier layer and a deep P+ plug emitter tie are added to the conventional IGBT structure. It is observed that the addition of the P+ plug alone results in a reduction in switching power losses and no change in V CE(sat), however the avalanche breakdown voltage (BV) and short circuit ruggedness of the device are improved. A further 0.4 V improvement in V CE(sat) is observed when the P+ plug is implemented in conjunction with an N hole barrier. This is accomplished without the usual degradation of BV and ruggedness normally associated with other N hole barrier structures. The design space of the new IGBT structure is thoroughly characterized using 2-D TCAD simulation. © 2012 IEEE.

Publication Date

5-31-2012

Publication Title

Conference Proceedings - IEEE SOUTHEASTCON

Number of Pages

-

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/SECon.2012.6196946

Socpus ID

84861513910 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84861513910

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