Clustering Of Flip-Flops For Useful-Skew Clock Tree Synthesis

Abstract

The clock network of a circuit is a main contributor to the power consumption of any ASIC design. A key technique that is used to reduce power consumption is to cluster flipflops or latches into groups and to place each group of flipflops close together to reduce the clock wire length. In this paper, we introduce a clock tree synthesis methodology that incorporates clustering with a previously published useful-skew clock tree synthesis technique to minimize the clock wire length. The clustering process is guided by bounded arrival time constraints, which enable its efficiency. Experimental results show that the proposed methodology reduces up to 34% of the total power consumption while meeting all timing constraints.

Publication Date

2-20-2018

Publication Title

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volume

2018-January

Number of Pages

507-512

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ASPDAC.2018.8297374

Socpus ID

85045327303 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85045327303

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