Pch Framework For Ip Runtime Security Verification

Abstract

Untrusted third-party vendors and manufacturers have raised security concerns in hardware supply chain. Among all existing solutions, formal verification methods provide powerful solutions in detection malicious behaviors at the pre-silicon stage. However, little work have been done towards built-in hardware runtime verification at the post-silicon stage. In this paper, a runtime formal verification framework is proposed to evaluate the trust of hardware during its execution. This framework combines the symbolic execution and SAT solving methods to validate the user defined properties. The proposed framework has been demonstrated on an FPGA platform using an SoC design with untrusted IPs. The experimentation results show that the proposed approach can provide high-level security assurance for hardware at runtime.

Publication Date

5-3-2018

Publication Title

Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2017

Volume

2018-May

Number of Pages

79-84

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/AsianHOST.2017.8353999

Socpus ID

85050934423 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85050934423

This document is currently not available here.

Share

COinS