Logic Locking Using Hybrid Cmos And Emerging Sinw Fets

Keywords

Emerging technology; Hardware security; Logic locking; Security metrics

Abstract

The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP) protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs) to replace the conventional Exclusive-OR (XOR)-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead.

Publication Date

9-20-2017

Publication Title

Electronics (Switzerland)

Volume

6

Issue

3

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.3390/electronics6030069

Socpus ID

85030244238 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85030244238

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