Logic Obfuscation Against Ic Reverse Engineering Attacks Using Plgs

Keywords

and obfuscated IC; IC reverse engineering; silicon nanowire FETs; untraceable design

Abstract

A strong logic locking approach could be utilized to contest serious threats on ICs. However, recent Boolean satisfiability (SAT) attack successfully decrypts all existing logic locking techniques. Even though different methods have been used to make the attack execution time increase exponentially, those methods are vulnerable to tracked and removed resilient SAT structure based attacks. In this work, we use silicon nanowire FETs to produce an obfuscated IC against reverse engineering attacks and reduce the performance penalty by exchanging some logic gates with different polymorphic gates based SiNW FETs and incorporating a small block of circuitry whose output is untraceable.

Publication Date

11-22-2017

Publication Title

Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017

Number of Pages

341-344

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ICCD.2017.59

Socpus ID

85030234918 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85030234918

This document is currently not available here.

Share

COinS