Novel Electrostatic Discharge (Esd) Clamp Circuit With Low Leakage Current

Abstract

A novel electrostatic discharge (ESD) clamp circuit for power-rail ESD protection, consisting of the stacked transistors and biased RC network, is proposed in a 90 nm CMOS process. The biased RC network possesses a small footprint and the detection circuit has a pretty low leakage current of up to 12 nA under normal operation. The proposed ESD clamp circuit has a long hold-on time of 800 ns under the ESD event and a quick turn-off mechanism for false triggering. SPICE simulation is carried out to evaluate the ESD clamp, and comparing with the conventional designs, the simulation results suggest that the proposed circuit has a lower power consumption and smaller footprint while achieving better performance.

Publication Date

10-5-2017

Publication Title

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volume

2017-July

Number of Pages

1-3

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/IPFA.2017.8060091

Socpus ID

85045069927 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85045069927

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