Title

Novel Voltage Triggered Electrostatic Discharge (Esd) Detection Circuit

Abstract

A novel 2×VDD-tolerant electrostatic discharge (ESD) detection circuit which uses only low-voltage devices is proposed in a 0.18 um CMOS process. Under normal operating conditions, all the devices are free from over-stress voltage threat. Our proposed detection circuit achieves a high triggering efficiency with a much smaller footprint. Comparing with the RC based detection circuit, our proposed circuit is a voltage triggered detection circuit which is immune to false triggering under the fast power-up events. SPICE simulation is carried out to evaluate the detection circuit, and the simulation results suggest that the proposed circuit could be used as a reliable 2×VDD-tolerant I/O buffer.

Publication Date

10-5-2017

Publication Title

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volume

2017-July

Number of Pages

1-4

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/IPFA.2017.8060071

Socpus ID

85045069069 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85045069069

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