Heterogeneous Stacking Silicon Controlled Rectifier Design With Improved Esd Performance

Abstract

A novel design consisting of a heterogeneous stacking of silicon control rectifier is proposed in this paper. A latch-up free design in a high voltage BCDMOS process is demonstrated. Structures based on this method are compared with conventionally stacked SCR structure. Comprehensive characterization, including DC and transmission line pulsing (TLP), is undertaken to demonstrate the performance.

Publication Date

10-5-2017

Publication Title

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volume

2017-July

Number of Pages

1-3

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/IPFA.2017.8060176

Socpus ID

85045051624 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85045051624

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