Title

Low Power In-Memory Computing Based On Dual-Mode Sot-Mram

Keywords

giant spin hall effect; In-memory computing; magnetic tunnel junction; memory architecture; SOT-MRAM

Abstract

In this paper, we propose a novel Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array design that could simultaneously work as non-volatile memory and implement a reconfigurable in-memory logic (AND, OR) without add-on logic circuits to memory chip as in traditional logic-in-memory designs. The computed logic output could be simply read out like a normal MRAM bit-cell using the shared memory peripheral circuits. Such intrinsic in-memory logic could be used to process data within memory to greatly reduce power-hungry and long distance data communication in conventional Von-Neumann computing systems. We further employ in-memory data encryption using Advanced Encryption Standard (AES) algorithm as a case study to demonstrate the efficiency of the proposed design. The device to architecture co-simulation results show that the proposed design can achieve 70.15% and 80.87% lower energy consumption compared to CMOS-ASIC and CMOL-AES implementations, respectively. It offers almost similar energy consumption as recent DW-AES implementation, but with 60.65% less area overhead.

Publication Date

8-11-2017

Publication Title

Proceedings of the International Symposium on Low Power Electronics and Design

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISLPED.2017.8009200

Socpus ID

85028583824 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85028583824

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