Title

Leveraging Spintronic Devices For Ultra-Low Power In-Memory Computing: Logic And Neural Network

Keywords

In-memory computing; In-memory data encryption; Neural network; Racetrack memory; Skyrmion; SOT-MRAM

Abstract

In-Memory computing has drawn many attentions as a promising solution to reduce massive power hungry data traffic between computing and memory units, leading to significant improvement of entire system performance and energy efficiency. Emerging spintronic device based non-volatile memory is becoming a next-generation universal memory candidate due to its non-volatility, zero leakage power in un-accessed bit-cell, high integration density, excellent endurance and compatibility with CMOS fabrication technology. In this paper, we present that different spintronic devices based memory, including spin-orbit torque magnetic random access memory (SOT-MRAM), magnetic racetrack memory, magnetic skyrmion, could be leveraged to implement an energy efficient inmemory computing platform. Then, we employ SOT-MRAM and racetrack memory to develop an efficient in-memory data encryption engine that could encrypt data within memory. Furthermore, we also show that emerging magnetic skyrmion device could be leveraged to design a tunable skyrmion neuron cluster that approximate non-linear neuron activation function, which is promising to achieve two orders of lower energy consumption compared with CMOS counterparts.

Publication Date

9-27-2017

Publication Title

Midwest Symposium on Circuits and Systems

Volume

2017-August

Number of Pages

1109-1112

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/MWSCAS.2017.8053122

Socpus ID

85034067054 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85034067054

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