Ultra‐Low‐Power Design And Hardware Security Using Emerging Technologies For Internet Of Things

Keywords

ADC; DPA; Emerging technologies; Hardware security; Neuromorphic computing; Side‐channel attack; Trojans; Tunnel FET; Ultra‐low power

Abstract

In this review article for Internet of Things (IoT) applications, important low‐power design techniques for digital and mixed‐signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non‐volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy‐constrained hardware security issues are reviewed. Specifically, light‐weight encryption‐based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all‐spin logic devices are highlighted. Furthermore, a novel ultra‐low power design using bio‐inspired neuromorphic computing and spiking neural network security are discussed.

Publication Date

9-8-2017

Publication Title

Electronics (Switzerland)

Volume

6

Issue

3

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.3390/electronics6030067

Socpus ID

85030248202 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85030248202

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