Evaluation Of Ldmos Figure Of Merit Using Device Simulation

Keywords

Breakdown voltage; Gate charge; LDMOS; R DS(on); STI; Super-junction

Abstract

The benefit of the super-junction (SJ) technique at the low-voltage (30 V) range is investigated in this work. Optimizations such as adding a buffer layer to the device have been used, but simulation and theoretical evidences show that the benefits of the SJ technique are marginal for 30 V applications. The floating P structure proved to be a good replacement for SJ devices at the 30 V range due to a simpler fabrication process as well as performance gains achieved with optimization. Also, a new idea of combining the floating P layer with a shallow trench isolation layer is proposed and simulated using TCAD, yielding the figure of merit (RDS(on) × QG) of 5.93 mΩ-nC, which is a 39% improvement on the standard floating P device.

Publication Date

5-1-2018

Publication Title

Electronics (Switzerland)

Volume

7

Issue

5

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.3390/electronics7050060

Socpus ID

85048231989 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85048231989

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