Keywords
Evolvable hardware, system on chip, genetic algorithm, universal digital block, puiseux series
Abstract
Intrinsic evolution of reconfigurable hardware is sought to solve computational problems using the intrinsic processing behavior of System-on-Chip (SoC) platforms. SoC devices combine capabilities of analog and digital embedded components within a reconfigurable fabric under software control. A new technique is developed for these fabrics that leverages the digital resources' enhanced accuracy and signal refinement capability to improve circuit performance of the analog resources' which are providing low power processing and high computation rates. In particular, Differential Digital Correction (DDC) is developed utilizing an error metric computed from the evolved analog circuit to reconfigure the digital fabric thereby enhancing precision of analog computations. The approach developed herein, Cascaded Digital Refinement (CaDR), explores a multi-level strategy of utilizing DDC for refining intrinsic evolution of analog computational circuits to construct building blocks, known as Constituent Functional Blocks (CFBs). The CFBs are developed in a cascaded sequence followed by digital evolution of higher-level control of these CFBs to build the final solution for the larger circuit at-hand. One such platform, Cypress PSoC-5LP was utilized to realize solutions to ordinary differential equations by first evolving various powers of the independent variable followed by that of their combinations to emulate mathematical series-based solutions for the desired range of values. This is shown to enhance accuracy and precision while incurring lower computational energy and time overheads. The fitness function for each CFB being evolved is different from the fitness function that is defined for the overall problem.
Notes
If this is your thesis or dissertation, and want to learn how to access it or for more information about readership statistics, contact us at STARS@ucf.edu
Graduation Date
2015
Semester
Spring
Advisor
DeMara, Ronald
Degree
Master of Science in Electrical Engineering (M.S.E.E.)
College
College of Engineering and Computer Science
Department
Electrical Engineering and Computer Science
Degree Program
Electrical Engineering
Format
application/pdf
Identifier
CFE0005723
URL
http://purl.fcla.edu/fcla/etd/CFE0005723
Language
English
Release Date
May 2015
Length of Campus-only Access
None
Access Status
Masters Thesis (Open Access)
STARS Citation
Thangavel, Vignesh, "Cascaded Digital Refinement for Intrinsic Evolvable Hardware" (2015). Electronic Theses and Dissertations. 1185.
https://stars.library.ucf.edu/etd/1185