Abstract

In H.264/AVC, DeBlocking Filter (DBF) achieves bit rate savings and it is used to improve visual quality by reducing the presence of blocking artifacts. However, these advantages come at the expense of increasing computational complexity of the DBF due to highly adaptive mode decision and small 4x4 block size. The DBF easily accounts for one third of the computational complexity of the decoder. The computational complexity required for various target applications from mobile to high definition video applications varies significantly. Therefore, it becomes apparent to design efficient architecture to adapt to different requirements. In this work, we exploit the scalability on both the hardware level and the algorithmic level to synergize the performance and to reduce computational complexity. First, we propose a modular DBF architecture which can be scaled to adapt to the required computing capability for various bit-rates, resolutions, and frame rates of video sequences. The scalable architecture is based on FPGA using dynamic partial reconfiguration. This desirable feature of FPGAs makes it possible for different hardware configurations to be implemented during run-time. The proposed design can be scaled to filter up to four different edges simultaneously, resulting in significant reduction of total processing time. Secondly, our experiments show by lowering the bit rate of video sequences, significant reduction in computational complexity can be achieved by the increased presence of skipped macroblocks, thus, avoiding redundant filtering operations. The implemented architecture has been evaluated using Xilinx Virtex-4 ML410 FPGA board. The design can operate at a maximum frequency of 103 MHz. The reconfiguration is done through Internal Configuration Access Port (ICAP) to achieve maximum performance needed by real time applications.

Notes

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Graduation Date

2010

Semester

Summer

Advisor

Lee, Jooheung

Degree

Master of Science in Computer Engineering (M.S.Cp.E.)

College

College of Engineering and Computer Science

Department

Electrical Engineering and Computer Science

Format

application/pdf

Identifier

CFE0003247

URL

http://purl.fcla.edu/fcla/etd/CFE0003247

Language

English

Release Date

August 2010

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Subjects

Dissertations, Academic -- Engineering and Computer Science, Engineering and Computer Science -- Dissertations, Academic

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