Keywords

Multiprocessors, Random access memory

Abstract

Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic mapping scheme over the fixed one. Results show that applications’ performance varies according to the mapping scheme used, and a dynamic mapping scheme achieves up to 2x increase in peak bandwidth utilization and around 30% higher energy efficiency than a system using only a single fixed scheme Moreover, the technique can be used to limit memory accesses into a subset of the memory devices by controlling data allocation at a finer granularity, providing a method to throttle main memory by allowing unaccessed devices to be put into power-down mode, hence saving power to meet a certain power budget.

Notes

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Graduation Date

2011

Semester

Fall

Advisor

Heinrich, Mark

Degree

Master of Science in Electrical Engineering (M.S.E.E.)

College

College of Engineering and Computer Science

Department

Electrical Engineering and Computer Science

Degree Program

Electrical Engineering

Format

application/pdf

Identifier

CFE0004121

URL

http://purl.fcla.edu/fcla/etd/CFE0004121

Language

English

Release Date

December 2011

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Subjects

Dissertations, Academic -- Engineering and Computer Science, Engineering and Computer Science -- Dissertations, Academic

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