Metal oxide semiconductors, Complementary, Power amplifiers
This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-toSource voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18µm CMOS technology process. A 50% decrease in the stress has been achieved in the Cascode class-F and Inverse class F amplifiers. The sensitivity and temperature effect were investigated using BSIM-4 model. Such an amplifier was designed and optimized for a good sensitivity. A substrate bias circuit was implemented to achieve a good sensitivity. Recommendations were made for future advancements for modification and optimization of the class F and inverse class F circuit by the application of other stress reduction strategies, and improvement of the substrate bias circuit for a better sensitivity.
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Yuan, Jiann S.
Master of Science in Electrical Engineering (M.S.E.E.)
College of Engineering and Computer Science
Electrical Engineering and Computer Science
Length of Campus-only Access
Masters Thesis (Open Access)
Dissertations, Academic -- Engineering and Computer Science, Engineering and Computer Science -- Dissertations, Academic
Skaria, Giji, "Class F And Inverse Class F Power Amplifier Subject To Electrical Stress Effect" (2011). Electronic Theses and Dissertations, 2004-2019. 1891.