Keywords

power amplifier, class-E, cascode, gate oxide, breakdown, oxide breakdown, model, TSMC, voltage stress, zero voltage switching

Abstract

This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.

Notes

If this is your thesis or dissertation, and want to learn how to access it or for more information about readership statistics, contact us at STARS@ucf.edu

Graduation Date

2010

Advisor

Yuan, Jiann S.

Degree

Master of Science in Electrical Engineering (M.S.E.E.)

College

College of Engineering and Computer Science

Department

Electrical Engineering and Computer Science

Degree Program

Electrical Engineering

Format

application/pdf

Identifier

CFE0003360

URL

http://purl.fcla.edu/fcla/etd/CFE0003360

Language

English

Release Date

August 2010

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Download

Share

COinS