Modeling short channel effect on high-k and stacked-gate MOSFETs

    Authors

    J. Zhang; J. S. Yuan;Y. Ma

    Abbreviated Journal Title

    Solid-State Electron.

    Keywords

    short channel effect; high-k stacked layer; threshold voltage; deep; submicron; gate dielectrics; surface roughness; DIELECTRICS; Engineering, Electrical & Electronic; Physics, Applied; Physics, ; Condensed Matter

    Abstract

    The roll-off of threshold voltage in deep submicron MOSFETs with high-k and stacked gate dielectrics is studied. A model to account for the fringing field effect on the high-k slacked layer dielectrics is proposed. The model predictions are compared with the two-dimensional device simulation. Good agreement between the model predictions and device simulation results has been obtained. (C) 2000 Elsevier Science Ltd. All rights reserved.

    Journal Title

    Solid-State Electronics

    Volume

    44

    Issue/Number

    11

    Publication Date

    1-1-2000

    Document Type

    Article

    Language

    English

    First Page

    2089

    Last Page

    2091

    WOS Identifier

    WOS:000165546700029

    ISSN

    0038-1101

    Share

    COinS