Self-protection capability of integrated NLDMOS power arrays in ESD pulse regimes

    Authors

    B. Aliaj; V. A. Vashchenko; A. Shibkov;J. J. Liou

    Comments

    Authors: contact us about adding a copy of your work at [email protected]

    Abbreviated Journal Title

    Microelectron. Reliab.

    Keywords

    Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied

    Abstract

    This paper provides a review of most recent cycle of studies of NLDMOS-based power arrays, their operation in ESD regimes, self-protection capability as well as the methods and measures to improve the array robustness on the device structure, layout architecture and array composition levels. Effective practices of improving ESD robustness at the cell level and backend level are presented followed by topology optimization. Discussion is based upon ESD characterization supported both by device-circuit mixed-mode and 2.5D array level simulations data. (C) 2011 Elsevier Ltd. All rights reserved.

    Journal Title

    Microelectronics Reliability

    Volume

    51

    Issue/Number

    12

    Publication Date

    1-1-2011

    Document Type

    Article

    Language

    English

    First Page

    2015

    Last Page

    2030

    WOS Identifier

    WOS:000298721500001

    ISSN

    0026-2714

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