Title

Delay Analysis Of Binmos Driver Including High Current Transients

Abstract

The BiNMOS gate delay analysis including high current transients has been developed. The modeling equations account for high electric field effect in the nMOS transistor and emitter crowding, base pushout, and base conductivity modulation in the bipolar transistor. In examining the switching transient of a BiNMOS driver, base pushout mechanism exhibits the detrimental effect on the gate propagation delay. The present circuit modeling methodology provides a fast turnaround design evaluation of sensitivity of process and device parameters into circuit performance. Computer simulation of a BiNMOS driver using the present analysis is compared with PISCES device simulation in support of physical reasoning. © 1992 IEEE

Publication Date

1-1-1992

Publication Title

IEEE Transactions on Electron Devices

Volume

39

Issue

3

Number of Pages

587-592

Document Type

Article

Identifier

scopus

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/16.123482

Socpus ID

0026836041 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0026836041

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