Title

Hot-Carrier-Induced Circuit Degradation For 0.18 Μm Cmos Technology

Abstract

Because the supply voltage is not proportional scaled with the device size, the further scaling down of CMOS devices is in turn accompanied with more and more severe hot-carrier reliability problems. Hot-carriers, the high energy carriers due to high electric field in the channel, are injected into the gate oxide or cause trapping states generation between Si and SiO2 interface, which is accumulated and cause long run reliability problems in devices and circuits. In this paper, we describe a systematic method to evaluate the circuit degradation due to hot-carrier stressing. First the substrate current and gate leakage current models are improved for more accuracy in predicting the lifetime of the devices and circuits. The hot-carrier stressing characterization is carried out for 0.18 μm technology. The circuit performance degradation is then evaluated using the parameters extracted from 0.18 μm technology for both digital logic circuits and RF circuits.

Publication Date

1-1-2001

Publication Title

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volume

2001-January

Number of Pages

284-289

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISQED.2001.915244

Socpus ID

50449101254 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/50449101254

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