Title
Electrostatic Discharge (Esd) Protection Challenges Of Gate-All-Around Nanowire Field-Effect Transistors
Abstract
Electrostatic discharge (ESD) performance, including trigger voltage, failure current, on-resistance and leakage current, of the gate-all-around silicon nanowire field-effect transistor depends on nanowire diameter, gate length and nanowire numbers. The device with best ESD robustness has medium gate length, small diameter and a large number of nanowires with multi-finger-multi-channel layout. ©The Electrochemical Society.
Publication Date
7-1-2011
Publication Title
ECS Transactions
Volume
34
Issue
1
Number of Pages
55-60
Document Type
Article; Proceedings Paper
Personal Identifier
scopus
DOI Link
https://doi.org/10.1149/1.3567559
Copyright Status
Unknown
Socpus ID
79959665120 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/79959665120
STARS Citation
Liu, W.; Liou, J. J.; Singh, N.; Lo, G. Q.; and Chung, J., "Electrostatic Discharge (Esd) Protection Challenges Of Gate-All-Around Nanowire Field-Effect Transistors" (2011). Scopus Export 2010-2014. 2550.
https://stars.library.ucf.edu/scopus2010/2550