Title

Failure Analysis Of Si Nanowire Field-Effect Transistors Subject To Electrostatic Discharge Stresses

Keywords

Degradation; electrostatic discharge (ESD); failure analysis; gate oxide breakdown; nanowire field-effect transistor (NW FET)

Abstract

The failure mechanisms of silicon nanowire field-effect transistors subject to electrostatic discharge (ESD) stresses are investigated using electrical characterization and microscopy analysis. Currentvoltage measurements are carried out before and after the devices are stressed with ESD equivalent pulses generated from the transmission line pulsing (TLP) tester. Depending on the TLP stress level, either a soft or a hard failure can take place in the nanowire devices due to the nondestructive damage or destructive fusing of nanowires and the surrounding gate oxide. © 2010 IEEE.

Publication Date

9-1-2010

Publication Title

IEEE Electron Device Letters

Volume

31

Issue

9

Number of Pages

915-917

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/LED.2010.2052911

Socpus ID

77956121413 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/77956121413

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